1. Field of the Invention
The present invention relates to a timing control circuit, timing generation system, timing control method and a semiconductor memory device, and more specifically to a timing control circuit, timing generation system and timing generation method suitable for generating a timing signal for a semiconductor memory device and a semiconductor memory device which includes the timing control circuit.
2. Description of Related Art
FIG. 20A is a diagram schematically showing a typical structure of a logic LSI chip. With reference to FIG. 20A, in the logic LSI chip (LOGIC), to increase throughput of the data processing, a pipeline operation is used where a flip-flop circuit (FF) divides the path from data input (DIN) to data output (DOUT) into a plurality of logical circuit blocks (LGK) and the flip-flop circuits (FF1, FF2 and FF3) are controlled by a clock signal (CK). Since the logical circuit blocks (LGK) can be divided in the manner that each of them has nearly the same delay in the logic LSI chip (LOGIC), the operation frequency can be increased as described above by the pipeline operation based on the flip-flop circuits (FF1, FF2 and FF3) controlled by a common clock signal. In the pipeline operation, the flip-flop circuit (FF) samples an output signal from the logical circuit block (LGK) at the previous stage in synchronization with the clock signal and outputs the sampled value to the logical circuit block (LGK) at the next stage, where an operation in each stage of the logical circuit blocks (LGK) is performed within one clock cycle.
FIG. 20B is a diagram schematically illustrating a typical structure of a clock-synchronous-type synchronous DRAM (SDRAM). In FIG. 20B, for simplicity, a flip-flop circuit at the input stage for sampling each of command (CMD) and address (ADD) is denoted by FF1 and a decoder for decoding command and address is denoted by DEC. With reference to FIG. 20B, in the synchronous DRAM (SDRAM), the flip-flop circuits FF1 at the command and address input stage and FF4 at the data output stage are controlled by (a rising edge of) the clock signal CK, while the other flip-flop circuits (for example FF2 and FF3) in the chip are controlled by a timing control signal generated by an analog delay circuit (ADLY1, ADLY2) in the timing control circuit (TG) by delaying a pulse generated by a pulse generator (PG) from the clock signal (CK) input from the external terminal.
In a synchronous DRAM, a delay in each of functional blocks in the chip, a decoder (DEC), a memory array (MEMCORE) and a data bus circuit (DB) differs substantially. Therefore, if their timings are controlled by a common clock signal, the operable clock frequency is determined by a delay in the memory array. Namely, in a synchronous DRAM, unlike the logic LSI chip in FIG. 20A, a delay in each functional block cannot be made almost the same and a pipeline operation using flip-flop circuits (FF) controlled by a common clock signal is impossible; therefore, it is difficult to increase the frequency.
A read operation is explained as an example of an operation performed by the synchronous DRAM shown in FIG. 20B. When command (CMD) and address (ADD) are input to the synchronous DRAM, each of them is received by the flip-flop circuit FF1 at the corresponding input stage in synchronization with the clock signal (CK). The command and address received by the FF1 are decoded by the decoder (DEC); an operation (a read operation in this case) and an address to be selected are determined. The analog delay circuit (ADLY1) delays the clock pulse from the pulse generator (PG) to coincide with this time (timing) and supplies the delayed clock pulse to the clock terminal (CK) of the next flip-flop circuit FF2; a main word line (MWLB) in the selected address is activated in the memory array (MEMCORE).
Then, the analog delay circuit (ADLY2) further delays the pulse delayed by the analog delay circuit (ADLY1) to coincide with a time at which a memory cell (not shown in the figure) selected in the memory array (MEMCORE) generates a signal in a bit line (not shown in the figure) and supplies it to the clock terminal CK of the flip-flop circuit FF3; a sense amplifier activation signal (SAN) is activated and the generated signal is amplified by a sense amplifier (not shown in the figure).
When the successive read command is input, the signal amplified by the sense amplifier (not shown in the figure) is transferred to the output buffer via the data bus circuit (DB); FF4 outputs the signal from the chip through the external data output terminal (DOUT) in synchronization with the clock signal from a counter circuit (COUNT).
Patent Document 1 etc. describes a structure comprising a coarse adjustment circuit for coarsely adjusting a clock phase and a fine adjustment circuit for finely adjusting the clock phase (The constitution described in the Patent Document 1 is extremely different from that of the present invention described in the following). Moreover, Patent Document 2 discloses a timing generation circuit comprising a first DLL (Delay Locked Loop) and a second DLL for supplying power voltage to a coarse delay unit and a fine delay unit in a serial connection, wherein the delay units used as a monitoring circuit for the first DLL and the second DLL have the same circuit form for the coarse delay unit and the fine delay unit.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2004-110490A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2006-186547A
[Non-Patent Document 1]
Kohtaroh Gotoh, Shigetoshi Wakayama, Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Yoshinori Okajima, and Masao Taguchi, ‘All-Digital Multi-Phase Delay Locked Loop for Internal Timing Generation in Embedded and/or High-Speed DRAMs’, 1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 107-108